(1) Field of the Invention
The present invention relates to semiconductor manufacturing and is more particularly directed to coding ROM (Read Only Memory) products to reduce mask cost and shorten product cycle time.
(2) Description of the Related Art
Nonvolatile read only memories or, ROMS, are programmed word by word (i.e., eight bits, or one byte, at a time) in contrast to random access memories, or RAMS, which are programmed one bit at a time. The first group of nonvolatile memories consists of those ROMs in which data is entered during manufacturing, and cannot subsequently be altered by the user. These devices are known as masked ROMs (or simply ROMS). The next category consists of memories which data can be entered by the user (user-programmable ROMS). In the first example of this type, known as programmable ROM, or PROM, data can be entered into the device only once. In the remaining ROM types, data can be erased as well as erased. In one class of erasable ROMS, the cells must be exposed to a strong ultraviolet light in order for stored data to be erased. These ROMs are called erasable-programmable ROMS, or EPROMs. In the final type, data can be electrically erased as well as entered into the device, these are referred to as EEPROMs.
Typically, masked ROM, or ROM, includes at least two types of devices with different threshold voltages in a wafer. A type of device is formed in an active area and another type of device with a threshold voltage mask formed in another active area during the process. For example, the first device is a normal device with threshold voltage Vt1 and another device with a threshold voltage Vt2, wherein the Vt1 is different from Vt2. Therefore, the second device needs an extra mask for ion implantation to obtain a different threshold voltage as provided with the first device. The method involves differentiating the threshold voltages by ion implantation of some of the transistor to different levels of threshold voltage. This method raises the threshold voltage of the n-channel device by doping boron with heavy dose. This method is so called threshold voltage programming. There are also the well known methods of field oxide programming and through-hole programming. The former method is introduced during manufacturing by using oxides of different thicknesses to differentiate between the different threshold voltages of the devices. In another method, the programming is achieved by selectively opening the contacts to the cells for the corresponding transistors and drains.
FIG. 1 is a cross-sectional view of a programmed cell for a typical prior art ROM device fabricated by the threshold voltage implant method. The threshold voltage implant method changes an enhancement mode n-channel metal oxide semiconductor field effect transistor (MOSFET) into a depletion mode device by implanting n-type ions into the channel region of the MOS transistor. The n-type implant programs or codes the transistor of the cell. In the present invention, however, p-type code is used for an enhancement mode n-channel MOS for the ROM process that is disclosed later in the embodiments of the invention.
The programmed cell shown in FIG. 1 includes a depletion mode MOS transistor in a semiconductor substrate (10). The programmed cell defines a p-type well region (20), field oxide regions (13), gate oxide region (30), and source/drain regions (15), (17). The programmed cell also defines an implanted channel region (19) under the gate oxide region (30). The implanted channel region changes the enhancement mode MOS transistor into the depletion mode transistor. A polysilicon gate (40), gate sidewall spacers (55), borophosphosilicate glass layer (50) (BPSG), metallization layer (60), and surface passivation (70) are also shown. The polysilicon gate, source region, drain region, and channel region define the depletion mode MOS-FET.
Each cell, such as the cell of FIG. 1, corresponds to a region for storing bits of information in a ROM semiconductor integrated circuit chip. Thousands and even millions of these microscopically small regions make up a core memory area (or active cell area) of the ROM chip. The completed ROM chip also includes peripheral circuits, interconnects, and bonding pad.
A method of programming or coding a mask-ROM is disclosed by Chiu, et al., in U.S. Pat. No. 5,538,914. The method includes forming gate oxide over the substrate between field oxide (FOX) regions; forming a control gate layer over the gate oxide; forming a gate mask over the device with and patterning a gate electrode and the gate oxide layer by etching through mask openings. Next, a lightly doped drain (LDD) mask is formed over the device exposing the gate. A P type dopant of a first dosage level is implanted through mask openings forming reverse type LDD implant doped P type regions. Spacers are next formed adjacent to the electrode over the substrate. An ion implant of N type dopant of a second dosage level is performed through the opening in the mask and aside from the spacers and the electrode into exposed portions of the substrate. The N type doped regions are self-aligned with the spacers and the gate and they provide a second dosage level in the substrate, the second dosage level being substantially different from the first dosage level.
Another method of forming a mask ROM is disclosed by Wu in U.S. Pat. No. 6,133,101. The method includes performing a blanket ion implantation to form regions LDD regions adjacent to gate structures. A second ion implantation is performed with tilted angle to form p channel punchthrough stopping regions. A third ion implantation is used to implant ions into a NMOS device region. Oxide spacers are then formed on gate structures. Next, a fourth ion implantation is then carried out to dope ions into the substrate to form source and drain regions in the NMOS region and a NMOS cell region, respectively. Next, a fifth ion implantation is used to dope dopant into a PMOS device region, thereby forming source and drain regions in the PMOS device region. Subsequently, a high temperature thermal anneal is performed to form shallow junction of the devices.
A different laminated gate mask ROM is shown in U.S. Pat. No. 6,087,699 by Wann, et al. A substrate is covered with a gate oxide layer between FOX regions with a blanket lower lamina for a gate on the surface. A mask-code mask has a window overlying the desired gate location. A doped code implant region is formed in the substrate by ion implanting code implant dopant through the mask. Following mask removal a blanket upper lamina of the gate covers the lower lamina. A gate mask covers the upper and lower laminae. The gate mask is patterned to protect the gate region over the device, leaving the remainder of the upper and lower lamina exposed. Exposed surfaces of the laminae are etched away leaving a laminated gate. LDD regions are formed in the substrate between the FOX regions and the gate by ion implanting dopant through portions of the gate oxide layer unprotected by the gate; forming spacers next to the gate; and forming source and drain regions in the substrate between the FOX regions and the spacers adjacent to the gate.
In U.S. Pat. No. 5,940,710 to Chung, et al., on the other hand, Chung et al teach a method for fabricating a metal oxide semiconductor field effect transistor (MOSFET) wherein source/drain junctions are formed by depositing and etching an oxide film having a desired thickness prior to the formation of a pocket region carried out by a pocket ion implantation after forming a gate oxide film and gate electrode on a channel region formed by implanting impurity ions in a silicon substrate. The pocket region is formed by impurity ions in source/drain regions exposed by etching the oxide film. Accordingly, it is possible to reduce the thermal budget applied to the source/drain junctions. As a result, the lateral diffusion of the impurity ions implanted in the source/drain junctions is sup-pressed yielding a channel longer than previously possible. Accordingly, the transistor achieves a highly compact or densely integrated size.
Still another memory device with multiple and orthogonally disposed conductors is disclosed in U.S. Pat. No. 5,480,822 by Hsue, et al. In accordance with this invention, a method of manufacture of a semiconductor memory device comprises the following steps: forming field oxide structures on a semiconductor substrate, forming a gate oxide layer on exposed surfaces of the substrate, forming a first word line layer on the device, patterning the first word line layer by forming a first patterned mask with a first set of openings therein and etching the first word line layer through the openings in the first mask to form conductor lines, forming a first dielectric layer on the surface of the first word line layer on the device, forming a second word line layer on the first dielectric layer, patterning the second word line layer by forming a second patterning mask with a second set of openings therein and etching portions of the second word line layer therethrough, forming a second dielectric layer on the surface of the second word line layer on the device, and implanting ions of dopant into predetermined locations into the semiconductor substrate of the device, the dopant being of sufficient concentration to form a doped region therein.
It is therefore an object of turning off a MOS transistor by performing an anti-code LDD implant.
It is another object of the present invention to provide a method of turning off a MOS transistor without high energy implant to cause any poly damage.
It is still another object of the present invention to provide a method of turning off a MOS transistor without being affected by the variation of the poly thickness.
It is yet another object of the present invention to provide a Flash-ROM process that is applicable to both polycide and silicide processes.
These objects are accomplished by providing a substrate having an NMOS region and a PMOS region; forming a dielectric layer over said substrate, including over said NMOS and PMOS regions; forming an NMOS gate electrode over said NMOS region and a PMOS gate electrode over said PMOS region over said dielectric layer formed over said NMOS and PMOS regions; forming a first cover layer over said PMOS region including over said PMOS gate electrode; performing an N-type lightly doped drain (NLDD) implant over uncovered said NMOS region using said NMOS gate electrode as a self-aligned mask; removing said first cover layer from over said PMOS region; forming a second cover layer over said NMOS region including over said NMOS gate electrode; performing P-type lightly doped drain (PLDD) implant over uncovered said PMOS region using said PMOS gate electrode as a self-aligned mask; removing said second cover layer from over said NMOS region; forming a third cover layer over said PMOS region including over said PMOS gate electrode; performing a code implant over uncovered said NMOS region using said NMOS gate electrode as a self-aligned mask; removing said third cover layer from over said PMOS region; forming a fourth cover layer over said NMOS region including over said NMOS gate electrode; performing a code implant over uncovered said PMOS region using said PMOS gate electrode as a self-aligned mask; removing said fourth cover layer from over said NMOS region; and performing a vertical and tilt angle anti-code LDD implant to turn off said MOS transistor.